Invention Grant
- Patent Title: Multilayered semiconductor device
- Patent Title (中): 多层半导体器件
-
Application No.: US14676735Application Date: 2015-04-01
-
Publication No.: US09251868B2Publication Date: 2016-02-02
- Inventor: Tetsuo Fukushi , Atsunori Hirobe , Muneaki Matsushige
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2014-078676 20140407
- Main IPC: G11C5/14
- IPC: G11C5/14 ; H01L23/50 ; H01L23/48 ; H01L23/00 ; H01L25/065 ; G11C5/06 ; G11C5/02

Abstract:
An object of the invention is to make effective use of the structure of a multilayered semiconductor device that uses penetration electrodes in such a manner that the layered chips obtain stable internal power supply voltages with no increase in current consumption or in the area of the layered chips. Internal power supply generation circuits furnished in each of the layered core chips have their outputs commonly coupled via electrodes penetrating the layered core chips. This allows electrical charges to be shared among the core chips, optimizes internal power consumption of the multilayered semiconductor device as a whole, and inhibits fluctuations in the internal power supply voltages.
Public/Granted literature
- US20150287441A1 MULTILAYERED SEMICONDUCTOR DEVICE Public/Granted day:2015-10-08
Information query