Invention Grant
US09251881B2 System and method to trim reference levels in a resistive memory
有权
修改电阻式存储器中的参考电平的系统和方法
- Patent Title: System and method to trim reference levels in a resistive memory
- Patent Title (中): 修改电阻式存储器中的参考电平的系统和方法
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Application No.: US14040332Application Date: 2013-09-27
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Publication No.: US09251881B2Publication Date: 2016-02-02
- Inventor: Taehyun Kim , Jung Pill Kim , Sungryul Kim
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Toler Law Group, PC
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/16 ; G11C13/00 ; G11C7/14 ; G11C11/15 ; G11C29/02

Abstract:
A system and method to trim reference levels in a resistive memory is disclosed. In a particular embodiment, a resistive memory includes multiple sets of reference cells. The resistive memory also includes a reference resistance measurement circuit. A first set of reference cells is accessible by the reference resistance measurement circuit to measure a first effective reference resistance corresponding to the first set of reference cells. A second set of reference cells is accessible by the reference resistance measurement circuit to measure a second effective reference resistance corresponding to the second set of reference cells. The resistive memory also includes a trimming circuit configured to set a reference resistance based on the measured first effective resistance and the measured second effective resistance.
Public/Granted literature
- US20150092469A1 SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY Public/Granted day:2015-04-02
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