Invention Grant
US09251881B2 System and method to trim reference levels in a resistive memory 有权
修改电阻式存储器中的参考电平的系统和方法

System and method to trim reference levels in a resistive memory
Abstract:
A system and method to trim reference levels in a resistive memory is disclosed. In a particular embodiment, a resistive memory includes multiple sets of reference cells. The resistive memory also includes a reference resistance measurement circuit. A first set of reference cells is accessible by the reference resistance measurement circuit to measure a first effective reference resistance corresponding to the first set of reference cells. A second set of reference cells is accessible by the reference resistance measurement circuit to measure a second effective reference resistance corresponding to the second set of reference cells. The resistive memory also includes a trimming circuit configured to set a reference resistance based on the measured first effective resistance and the measured second effective resistance.
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