Invention Grant
US09252027B1 Method of forming pattern, manufacturing method of semiconductor device and template
有权
形成图案的方法,半导体器件和模板的制造方法
- Patent Title: Method of forming pattern, manufacturing method of semiconductor device and template
- Patent Title (中): 形成图案的方法,半导体器件和模板的制造方法
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Application No.: US14644880Application Date: 2015-03-11
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Publication No.: US09252027B1Publication Date: 2016-02-02
- Inventor: Yusuke Kasahara , Kei Kobayashi
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2014-186514 20140912
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L21/475 ; H01L21/02

Abstract:
In accordance with an embodiment, a method of forming a pattern includes forming a first layer on a fabrication target film, making a mold and the first layer push each other to form a protrusion on the fabrication target film, and forming first and second regions, forming a block copolymer layer including first and second blocks in the first and second regions, phase-separating the block copolymer layer, forming second and third layers in the first region, and forming fourth and fifth layers in the second region; and removing the third and fifth layers. The first region is surrounded by the first layer and the protrusion. The second region is surrounded by the first layer and contacts the first region via the protrusion. The third layer is surrounded by the second layer. The fifth layer is surrounded by the fourth layer.
Information query
IPC分类: