Invention Grant
- Patent Title: Metal and via definition scheme
- Patent Title (中): 金属和通孔定义方案
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Application No.: US14191169Application Date: 2014-02-26
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Publication No.: US09252048B2Publication Date: 2016-02-02
- Inventor: Yen-Cheng Lu , Chih-Tsung Shih , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/768

Abstract:
A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer.
Public/Granted literature
- US20150072519A1 Metal and Via Definition Scheme Public/Granted day:2015-03-12
Information query
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