Invention Grant
- Patent Title: Semiconductor device having multilayer wiring structure and manufacturing method of the same
- Patent Title (中): 具有多层布线结构的半导体器件及其制造方法
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Application No.: US13235782Application Date: 2011-09-19
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Publication No.: US09252099B2Publication Date: 2016-02-02
- Inventor: Kazuyoshi Arai
- Applicant: Kazuyoshi Arai
- Applicant Address: JP Yokohama, Kanagawa
- Assignee: TERA PROBE, INC.
- Current Assignee: TERA PROBE, INC.
- Current Assignee Address: JP Yokohama, Kanagawa
- Agency: Holtz, Holtz & Volek PC
- Priority: JP2010-220481 20100930
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/522 ; H01L23/31 ; H01L25/065 ; H01L25/00 ; H01L25/16 ; H01L23/00
Abstract:
Disclosed is a semiconductor device 1 comprising: a semiconductor chip 10; a multilayer wiring structure 30 stacked on the semiconductor chip 10; and an electronic component 60,80 embedded in the multilayer wiring structure 30.
Public/Granted literature
- US20120080788A1 SEMICONDUCTOR DEVICE HAVING MULTILAYER WIRING STRUCTURE AND MANUFACTURING METHOD OF THE SAME Public/Granted day:2012-04-05
Information query
IPC分类:
