Method for forming semiconductor layout

Invention Grant

US09252115B1 Method for forming semiconductor layout 有权

Title translation: 半导体布局形成方法

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Patent Title: Method for forming semiconductor layout
Patent Title (中): 半导体布局形成方法
Application No.: US14331624

Application Date: 2014-07-15
Publication No.: US09252115B1

Publication Date: 2016-02-02
Inventor: Thomas Ngo , Shiann-Ming Liou
Applicant: Marvell International Ltd.
Applicant Address: BM Hamilton
Assignee: Marvell International Ltd.
Current Assignee: Marvell International Ltd.
Current Assignee Address: BM Hamilton
Main IPC: H01L21/44
IPC: H01L21/44 ; H01L21/48 ; H01L23/00 ; H01L21/768

Abstract:

Apparatuses and methods for an improved semiconductor layout are described herein. Embodiments of the present invention provide a microelectronic device including a microelectronic die and one or more redistribution paths formed thereon for electrically interconnecting at least one bond pad with an exposed portion of the redistribution path. The redistribution paths, bond pads, and exposed portions may be configured to result in the device having a width narrowed by at least the width of the bond pads due to their absence on at least one edge.

Abstract(Chinese):

本文描述了用于改进的半导体布局的装置和方法。本发明的实施例提供了一种包括微电子管芯和在其上形成的一个或多个再分布路径的微电子器件，用于将至少一个接合焊盘与再分配路径的暴露部分电互连。再分布路径，接合焊盘和暴露部分可以被配置为导致器件的宽度由于它们在至少一个边缘上的缺失而至少缩小了接合焊盘的宽度。

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IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/44	....用H01L21/36至H01L21/428各组不包含的方法或设备在半导体材料上制造电极的