Invention Grant
- Patent Title: Test structure and method for determining overlay accuracy in semiconductor devices using resistance measurement
- Patent Title (中): 使用电阻测量确定半导体器件的覆盖精度的测试结构和方法
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Application No.: US13215908Application Date: 2011-08-23
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Publication No.: US09252202B2Publication Date: 2016-02-02
- Inventor: Daniel Piper
- Applicant: Daniel Piper
- Applicant Address: US WA Camas
- Assignee: WAFERTECH, LLC
- Current Assignee: WAFERTECH, LLC
- Current Assignee Address: US WA Camas
- Agency: Duane Morris LLP
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L49/02

Abstract:
Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.
Public/Granted literature
Information query
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