Invention Grant
US09252215B2 Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device
有权
半导体绝缘体finFET器件上的约束外延源极/漏极区域
- Patent Title: Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device
- Patent Title (中): 半导体绝缘体finFET器件上的约束外延源极/漏极区域
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Application No.: US14827535Application Date: 2015-08-17
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Publication No.: US09252215B2Publication Date: 2016-02-02
- Inventor: Brian J. Greene , Arvind Kumar , Dan M. Mocuta
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Steven Meyers
- Main IPC: H01L29/161
- IPC: H01L29/161 ; H01L29/20 ; H01L29/08 ; H01L29/78 ; H01L29/06 ; H01L29/16 ; H01L29/165

Abstract:
A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins on an insulator layer of a semiconductor substrate, and forming a plurality of gate stacks on the insulator layer. Each gate stack wraps around a respective portion of the semiconductor fins. The method further includes forming a dielectric layer on the insulator layer. The dielectric layer fills voids between the semiconductor fins and gate stacks, and covers the semiconductor fins. The method further includes etching at least one portion of the semiconductor fins until reaching the insulator layer such that at least one cavity is formed. The cavity exposes seed regions of the semiconductor fins located between adjacent gate stacks. The method further includes epitaxially growing a semiconductor material from the seed regions to form source/drain regions corresponding to a respective gate stack.
Public/Granted literature
- US20150357412A1 CONSTRAINED EPITAXIAL SOURCE/DRAIN REGIONS ON SEMICONDUCTOR-ON-INSULATOR FINFET DEVICE Public/Granted day:2015-12-10
Information query
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