Invention Grant
- Patent Title: Shielded gate trench MOS with improved source pickup layout
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Application No.: US14660361Application Date: 2015-03-17
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Publication No.: US09252265B2Publication Date: 2016-02-02
- Inventor: Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
- Applicant: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee Address: US CA Sunnyvale
- Agency: JDI Patent
- Agent Joshua D. Isenberg
- Main IPC: H01L29/772
- IPC: H01L29/772 ; H01L29/78 ; H01L21/283 ; H01L27/088 ; H01L29/40 ; H01L29/417 ; H01L29/66 ; H01L29/423 ; H01L21/265 ; H01L29/45 ; H01L29/49 ; H01L29/10

Abstract:
A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
Public/Granted literature
- US20150194522A1 SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT Public/Granted day:2015-07-09
Information query
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