There are provided stage circuits and a scan driver using the same, which can supply scan signals using a simultaneous method or an interlace method. Each of the stage circuits includes a progressive driver and a simultaneous driver. The progressive driver outputs a scan signal to an output terminal, corresponding to a plurality of clock signals supplied simultaneously or progressively, and the coupling between the progressive driver and the output terminal is blocked when a third control signal is supplied. The simultaneous driver outputs a scan signal to the output terminal, corresponding to first and second control signals which do not overlap each other, and the coupling between the simultaneous driver and the output terminal is blocked when a fourth control signal, which does not overlap the third control signal, is supplied.