Invention Grant
US09255966B2 Receiver circuit, semiconductor integrated circuit, and test method
有权
接收机电路，半导体集成电路和测试方法
- Patent Title: Receiver circuit, semiconductor integrated circuit, and test method
- Patent Title (中): 接收机电路，半导体集成电路和测试方法
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Application No.: US14176901Application Date: 2014-02-10
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Publication No.: US09255966B2Publication Date: 2016-02-09
- Inventor: Mitsuru Onodera
- Applicant: SOCIONEXT INC.
- Applicant Address: JP Yokohama
- Assignee: SOCIONEXT INC.
- Current Assignee: SOCIONEXT INC.
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2013-049807 20130313
- Main IPC: G01R31/317
- IPC: G01R31/317 ; H04L1/20
Abstract:
A receiver circuit includes a CDR circuit, a jitter generator unit, a test pattern generator unit, and a comparator unit. The jitter generator unit generates jitter having first characteristics (frequency and amplitude). The test pattern generator unit generates a test pattern to which the jitter is added, and supplies the test pattern to the CDR circuit. The comparator unit compares a value outputted from the CDR circuit with an expected value and outputs a comparison result.
Public/Granted literature
- US20140269872A1 RECEIVER CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND TEST METHOD Public/Granted day:2014-09-18
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