Example embodiments of an apparatus to reduce power consumed by a processor include a timing signal block configured to be coupled to measure the magnitude of an alternating current voltage signal supplied to a processor and to assert a timing signal when the magnitude of the alternating current voltage signal is about equal to zero volts and a throttling block configured to be coupled to the processor, to receive the timing signal and to assert a throttling signal that causes processor speed to be reduced so that processor power consumption is reduced in phase with the alternating current voltage signal and harmonic distortion of a current waveform supplied to the processor is reduced.