A memory includes a cell array including memory cells storing data, and a write driver writing data to the cells. A write driver performs or does not perform writing of write data according to write mask data input along with the write data. A multiplexer selectively outputs a write protect signal or the write mask data. The write protect signal is fixed to a command prohibiting the write data from being written. The command is included in the write mask data. A write protect controller controls the multiplexer to output the write protect signal when an address of a write protect area in the cell array matches an address of the write data. The write protect controller controls the multiplexer to output the write mask data as it is when the address of the write protect area in the cell array does not match the address of the write data.