Invention Grant
- Patent Title: Data processor chip with flexible bus system
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Application No.: US14718516Application Date: 2015-05-21
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Publication No.: US09256575B2Publication Date: 2016-02-09
- Inventor: Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
- Applicant: PACT XPP TECHNOLOGIES AG
- Applicant Address: DE Munich
- Assignee: PACT XPP TECHNOLOGIES AG
- Current Assignee: PACT XPP TECHNOLOGIES AG
- Current Assignee Address: DE Munich
- Agent Edward P. Heller, III
- Priority: WOPCT/EP00/10516 20001009; DE10110530 20010305; DE10111014 20010307; DE10135210 20010724; DE10135211 20010724; DE10139170 20010816; DE10142231 20010829; DE10142894 20010903; DE10142903 20010903; DE10142904 20010903; DE10144732 20010911; DE10144733 20010911; DE10145792 20010917; DE10145795 20010917; DE10146132 20010919; WOPCT/EP01/11299 20010930
- Main IPC: G06F7/52
- IPC: G06F7/52 ; G06F15/80 ; G06F15/78 ; G06F9/30 ; G06F13/40
Abstract:
A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.
Public/Granted literature
- US20150261722A1 Data processor chip with flexible bus system Public/Granted day:2015-09-17
Information query
