Invention Grant
- Patent Title: Method for integrated circuit mask patterning
- Patent Title (中): 集成电路掩模图案化方法
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Application No.: US14180233Application Date: 2014-02-13
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Publication No.: US09256709B2Publication Date: 2016-02-09
- Inventor: Jue-Chin Yu , Lun Hsieh , Pi-Tsung Chen , Shuo-Yen Chou , Ru-Gun Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Provided is a method of transforming an integrated circuit (IC) pattern into one or more patterns suitable for subsequent processing, such as mask fabrication. The method includes receiving an IC pattern that has an arbitrary shape, and using a computer, deriving an approximation IC pattern, wherein the approximation IC pattern is in a shape that is a user-defined fabrication-friendly shape, such as a rectangle or an ellipse. The method further includes calculating a pattern approximation error between the IC pattern and the approximation IC pattern. The method further includes checking whether the pattern approximation error is less than a user-defined threshold. If it is, the method further includes outputting the approximation IC pattern for subsequent fabrication. Otherwise, the method further includes splitting the IC pattern into a plurality of subparts, and recursively transforming each of the plurality of subparts.
Public/Granted literature
- US20150227671A1 Method For Integrated Circuit Mask Patterning Public/Granted day:2015-08-13
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