A semiconductor memory device, including a plurality of pairs of bit lines; a plurality of memory cells coupled to a plurality of word lines and the plurality of pairs of bit lines; a plurality of sense amplifiers each coupled between a corresponding pair of bit lines; a plurality of first driver transistors coupled between at least one of the sense amplifiers and a first power supply line; a plurality of second driver transistors coupled between at least two of the sense amplifiers and a second power supply line; a pair of common data lines; a plurality of column selection gates each coupled between a corresponding one of pair of bit lines and a corresponding one of pair of common data lines, and a plurality of mask selection gates each coupled between a corresponding one of pair of bit lines and a corresponding one of column selection gates.