DDR PHY interface bit error testing and training is provided for Double Data Rate memory systems. An integrated circuit comprises a bit error test (BERT) controller that provides a bit pattern; and a physical interface having a plurality of byte lanes. A first byte lane is connected by a loopback path to a second byte lane and the BERT controller writes the bit pattern that is obtained using the loopback path to evaluate the physical interface. The evaluation comprises (i) a verification that the bit pattern was properly written and read; (ii) a gate training process to position an internal gate signal; (iii) a read leveling training process to position both edges of a strobe signal; and/or (iv) a write bit de-skew training process to align a plurality of bits within a given byte lane.