Invention Grant
- Patent Title: Method of semiconductor integrated circuit fabrication
- Patent Title (中): 半导体集成电路制造方法
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Application No.: US14268130Application Date: 2014-05-02
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Publication No.: US09257282B2Publication Date: 2016-02-09
- Inventor: Chih-Tsung Shih , Tsung-Min Huang , Chung-Ju Lee , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/033 ; H01L21/02
Abstract:
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is formed over a substrate. An interlayer is formed over the dielectric layer. A first photoresist layer with a first opening is formed over the interlayer and a second photoresist layer having a second opening is formed over the first photoresist layer. Spacers are formed along sidewalls of the first opening and the second opening. A first trench is formed in the interlayer by using the spacer along the first opening as an etch mask. A second trench is formed in the interlayer by using the spacer along the second opening as an etch mask. The first trench and the second trench are extended down into the dielectric layer as a lower portion and an upper portion, respectively, of a dielectric trench.
Public/Granted literature
- US20150318173A1 Method of Semiconductor Integrated Circuit Fabrication Public/Granted day:2015-11-05
Information query
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