Invention Grant
- Patent Title: Lowering parasitic capacitance of replacement metal gate processes
- Patent Title (中): 降低替代金属栅极工艺的寄生电容
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Application No.: US14197959Application Date: 2014-03-05
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Publication No.: US09257289B2Publication Date: 2016-02-09
- Inventor: Effendi Leobandung , Vijay Narayanan
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Louis J. Percello
- Main IPC: H01L21/22
- IPC: H01L21/22 ; H01L21/28 ; H01L29/49 ; H01L29/51

Abstract:
The present disclosure provides a method of forming a gate structure of a semiconductor device with reduced gate-contact parasitic capacitance. In a replacement gate scheme, a high-k gate dielectric layer is deposited on a bottom surface and sidewalls of a gate cavity. A metal cap layer and a sacrificial cap layer are deposited sequentially over the high-k gate dielectric layer to form a material stack. After ion implantation in vertical portions of the sacrificial cap layer, at least part of the vertical portions of the material stack is removed. The subsequent removal of a remaining portion of the sacrificial cap layer provides a gate component structure. The vertical portions of the gate component structure do not extend to a top of the gate cavity, thereby significantly reducing gate-contact parasitic capacitance.
Public/Granted literature
- US20150255294A1 LOWERING PARASITIC CAPACITANCE OF REPLACEMENT METAL GATE PROCESSES Public/Granted day:2015-09-10
Information query
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