Invention Grant
- Patent Title: Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
- Patent Title (中): 利用多个无凸起积聚结构和硅通孔的微电子封装
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Application No.: US13996839Application Date: 2012-05-14
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Publication No.: US09257368B2Publication Date: 2016-02-09
- Inventor: Eng Huat Goh , Hoay Tien Teoh
- Applicant: Eng Huat Goh , Hoay Tien Teoh
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- International Application: PCT/US2012/037787 WO 20120514
- International Announcement: WO2013/172814 WO 20131121
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L21/50 ; H01L23/00 ; H01L23/29 ; H01L23/538
Abstract:
A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.
Public/Granted literature
- US20140021635A1 MICROELECTRIC PACKAGE UTILIZING MULTIPLE BUMPLESS BUILD-UP STRUCTURES AND THROUGH-SILICON VIAS Public/Granted day:2014-01-23
Information query
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