Invention Grant
- Patent Title: Semiconductor device
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Application No.: US14645899Application Date: 2015-03-12
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Publication No.: US09257371B2Publication Date: 2016-02-09
- Inventor: Chikako Imura , Koichi Kanemoto
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: JP2012-209656 20120924
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/00

Abstract:
A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN.
Public/Granted literature
- US20150187682A1 SEMICONDUCTOR DEVICE Public/Granted day:2015-07-02
Information query
IPC分类: