Invention Grant
US09257406B2 On-chip interconnects with reduced capacitance and method of fabrication thereof 有权
具有减小的电容的片上互连及其制造方法

On-chip interconnects with reduced capacitance and method of fabrication thereof
Abstract:
An electronics interconnection system is provided with reduced capacitance between a signal line and the surrounding dielectric material. By using a non-homogenous dielectric, the effective dielectric loss of the material is reduced. This reduction results in less power loss from the signal line to the dielectric material, which reduces the number of buffers needed on the signal line. This increases the speed of the signal, and reduces the power consumed by the interconnection system. The fabrication techniques provided are advantageous because they can be fabricated using today's standard IC fabrication techniques.
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