Invention Grant
- Patent Title: On-chip interconnects with reduced capacitance and method of fabrication thereof
- Patent Title (中): 具有减小的电容的片上互连及其制造方法
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Application No.: US14269117Application Date: 2014-05-03
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Publication No.: US09257406B2Publication Date: 2016-02-09
- Inventor: Achyut Kumar Dutta
- Applicant: Achyut Kumar Dutta
- Applicant Address: US CA Santa Clara
- Assignee: Banpil Photonics, Inc.
- Current Assignee: Banpil Photonics, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H01L23/00 ; H01L23/473 ; H01L23/522 ; H01L23/532 ; H01L21/768 ; H01L21/3105 ; H01L21/321

Abstract:
An electronics interconnection system is provided with reduced capacitance between a signal line and the surrounding dielectric material. By using a non-homogenous dielectric, the effective dielectric loss of the material is reduced. This reduction results in less power loss from the signal line to the dielectric material, which reduces the number of buffers needed on the signal line. This increases the speed of the signal, and reduces the power consumed by the interconnection system. The fabrication techniques provided are advantageous because they can be fabricated using today's standard IC fabrication techniques.
Public/Granted literature
- US20150014859A1 ON-CHIP INTERCONNECTS WITH REDUCED CAPACITANCE AND METHOD OF FABRICATION THEREOF Public/Granted day:2015-01-15
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