Invention Grant
- Patent Title: Stacked semiconductor structure and method
- Patent Title (中): 叠层半导体结构及方法
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Application No.: US14250024Application Date: 2014-04-10
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Publication No.: US09257414B2Publication Date: 2016-02-09
- Inventor: Szu-Ying Chen , Meng-Hsun Wan , Dun-Nian Yaung
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L25/065 ; H01L25/00 ; H01L23/00

Abstract:
A method for forming a stacked semiconductor structure comprises providing a first chip comprising a plurality of first active circuits and a first aluminum connection pad, depositing a first dielectric layer on a first side of the first chip, forming a first copper bonding pad on the first aluminum connection pad, providing a second chip comprising a plurality of second active circuits, depositing a second dielectric layer on a first side of the second chip, forming a second copper bonding pad in the second dielectric layer, stacking the first chip on the second chip, wherein the first copper bonding pad is in direct contact with the second copper bonding pad and bonding the first chip and the second chip to form a uniform bonded feature.
Public/Granted literature
- US20150294955A1 Stacked Semiconductor Structure and Method Public/Granted day:2015-10-15
Information query
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