Invention Grant
- Patent Title: Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
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Application No.: US14706359Application Date: 2015-05-07
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Publication No.: US09257415B2Publication Date: 2016-02-09
- Inventor: Michael B. Vincent , Scott M. Hayes , Jason R. Wright , Zhiwei Gong
- Applicant: Michael B. Vincent , Scott M. Hayes , Jason R. Wright , Zhiwei Gong
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR INC.
- Current Assignee: FREESCALE SEMICONDUCTOR INC.
- Current Assignee Address: US TX Austin
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L23/498 ; H01L23/538 ; H01L25/10 ; H01L23/31 ; H01L21/56 ; H01L21/48 ; H01L25/00 ; H01L25/03

Abstract:
Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.
Public/Granted literature
- US20150243635A1 STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF Public/Granted day:2015-08-27
Information query
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