Invention Grant
- Patent Title: Integrated high-k/metal gate in CMOS process flow
- Patent Title (中): 集成高k /金属门CMOS工艺流程
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Application No.: US14482870Application Date: 2014-09-10
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Publication No.: US09257426B2Publication Date: 2016-02-09
- Inventor: Ryan Chia-Jen Chen , Yi-Shien Mor , Yi-Hsing Chen , Kuo-Tai Huang , Chien-Hao Chen , Yih-Ann Lin , Jr Jung Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L27/092 ; H01L21/28 ; H01L21/8238 ; H01L29/49 ; H01L29/51 ; H01L29/06 ; H01L29/423
Abstract:
A semiconductor device includes a semiconductor substrate that has a first-type active region and a second-type active region, a dielectric layer over the semiconductor substrate, a first metal layer having a first work function formed over the dielectric layer, the first metal layer being at least partially removed from over the second-type active region, a second metal layer over the first metal layer in the first-type active region and over the dielectric layer in the second-type active region, the second metal layer having a second work function, and a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region.
Public/Granted literature
- US20150061031A1 Integrated High-K/Metal Gate In CMOS Process Flow Public/Granted day:2015-03-05
Information query
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