Invention Grant
US09257445B2 Method of making a split gate non-volatile memory (NVM) cell and a logic transistor
有权
分离门非易失性存储器(NVM)单元和逻辑晶体管的制造方法
- Patent Title: Method of making a split gate non-volatile memory (NVM) cell and a logic transistor
- Patent Title (中): 分离门非易失性存储器(NVM)单元和逻辑晶体管的制造方法
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Application No.: US14291224Application Date: 2014-05-30
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Publication No.: US09257445B2Publication Date: 2016-02-09
- Inventor: Konstantin V. Loiko , Brian A. Winstead
- Applicant: Konstantin V. Loiko , Brian A. Winstead
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L27/115 ; H01L21/285 ; H01L29/423 ; H01L21/28 ; H01L29/78 ; H01L29/66

Abstract:
Semiconductor structures and methods for making semiconductor structures include a split gate non-volatile memory (NVM) cell in an NVM region. A charge storage layer, a first conductive layer, and a capping layer are formed over the substrate, which are patterned to form a control gate stack in the NVM region of the substrate. A high-k dielectric layer, a metal layer, and a second conductive layer are formed over the substrate. The second conductive layer and the metal layer are patterned to form remaining portions of the second conductive layer and the metal layer over and adjacent to a first side of the control gate stack. The remaining portion of the second conductive layer is removed to form a select gate stack, which includes the remaining portion of the metal layer. A stressor layer is formed over the substrate.
Public/Granted literature
- US20150348985A1 METHOD OF MAKING A SPLIT GATE NON-VOLATILE MEMORY (NVM) CELL AND A LOGIC TRANSISTOR Public/Granted day:2015-12-03
Information query
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