Invention Grant
US09257527B2 Nanowire transistor structures with merged source/drain regions using auxiliary pillars
有权
具有合并源极/漏极区域的纳米线晶体管结构使用辅助柱
- Patent Title: Nanowire transistor structures with merged source/drain regions using auxiliary pillars
- Patent Title (中): 具有合并源极/漏极区域的纳米线晶体管结构使用辅助柱
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Application No.: US14181564Application Date: 2014-02-14
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Publication No.: US09257527B2Publication Date: 2016-02-09
- Inventor: Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Otterstedt, Ellenbogen & Kammer, LLP
- Agent Louis J. Percello
- Main IPC: H01L29/775
- IPC: H01L29/775 ; H01L29/66 ; H01L29/423 ; H01L21/02 ; H01L29/786 ; H01L29/06

Abstract:
A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures.
Public/Granted literature
- US20150236120A1 NANOWIRE TRANSISTOR STRUCTURES WITH MERGED SOURCE/DRAIN REGIONS USING AUXILIARY PILLARS Public/Granted day:2015-08-20
Information query
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