Invention Grant
US09257897B2 Circuit arrangement for protecting electronic devices against incorrect logic voltages
有权
用于保护电子设备免受不正确逻辑电压的电路布置
- Patent Title: Circuit arrangement for protecting electronic devices against incorrect logic voltages
- Patent Title (中): 用于保护电子设备免受不正确逻辑电压的电路布置
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Application No.: US12604605Application Date: 2009-10-23
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Publication No.: US09257897B2Publication Date: 2016-02-09
- Inventor: Klaus-Peter Saeck , Thomas Warneke , Viktor Oster
- Applicant: Klaus-Peter Saeck , Thomas Warneke , Viktor Oster
- Applicant Address: DE
- Assignee: Phoenix Contact GmbH & Co. KG
- Current Assignee: Phoenix Contact GmbH & Co. KG
- Current Assignee Address: DE
- Agency: Kaplan Breyer Schwarz & Ottesen, LLP
- Priority: DE102008053702 20081029
- Main IPC: H02H7/10
- IPC: H02H7/10 ; H02M1/32 ; H02M3/02

Abstract:
The invention is based on the problem of devising a circuit arrangement (10) for protecting electronic devices from incorrect logic voltages, wherein this circuit arrangement delivers increased protection against overvoltages, so that this circuit arrangement could also be used in multi-channel fail-safe systems that satisfy, for example, Performance Level “e” according to DIN EN ISO 13849. The circuit arrangement (10) has an input terminal (80) for connecting a power supply device and at least one voltage converter (90) that delivers, on the output side, an adjustable logic voltage. A controllable switching element (70) is connected between the one or more voltage converters (90, 95) and the input terminal (80). Furthermore, a first monitoring device (20) is provided for monitoring the logic voltage. The first monitoring device (20) is constructed so that it triggers the opening of the switching element (70) when the logic voltage reaches or exceeds a predetermined threshold.
Public/Granted literature
- US20100103567A1 Circuit arrangement for protecting electronic devices against incorrect logic voltages Public/Granted day:2010-04-29
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