Invention Grant
- Patent Title: Phase locked loop
- Patent Title (中): 锁相环
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Application No.: US14050691Application Date: 2013-10-10
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Publication No.: US09257998B2Publication Date: 2016-02-09
- Inventor: Tsung-Hsien Tsai
- Applicant: Taiwan Semiconductor Manufacturing Co., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H03L7/093
- IPC: H03L7/093

Abstract:
A circuit includes a phase locked loop and a logic IC. The phase locked loop is coupled to the logic IC. The logic IC is configured for generating an adaptive residue according to a first parameter and a second parameter. The phase locked loop is configured for providing the first parameter and the second parameter, and the phase locked loop generates an oscillator signal based on the adaptive residue.
Public/Granted literature
- US20150102845A1 Phase Locked Loop Public/Granted day:2015-04-16
Information query
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