Invention Grant
US09258224B2 Packet processing VLIW action unit with or-multi-ported instruction memory
有权
分组处理具有或多端口指令存储器的VLIW动作单元
- Patent Title: Packet processing VLIW action unit with or-multi-ported instruction memory
- Patent Title (中): 分组处理具有或多端口指令存储器的VLIW动作单元
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Application No.: US14190770Application Date: 2014-02-26
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Publication No.: US09258224B2Publication Date: 2016-02-09
- Inventor: Patrick W. Bosshart , Hun-Seok Kim
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Frank D. Cimino
- Main IPC: H04L12/28
- IPC: H04L12/28 ; H04L12/56 ; H04L12/741 ; H04L12/935 ; H04L12/743
Abstract:
An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.
Public/Granted literature
- US20140241359A1 PACKET PROCESSING VLIW ACTION UNIT WITH OR-MULTI-PORTED INSTRUCTION MEMORY Public/Granted day:2014-08-28
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