A phase interpolation clock generator includes: a phase detector configured to detect a phase difference between an input signal and a clock; a phase control signal generator configured to generate a phase control signal that is inverted for a certain phase difference and changes between a high level and a low level based on the phase difference; a controller configured to generate a combining control signal for combining a plurality of phase clocks and performing phase interpolation based on the phase control signal; an overshoot detector configured to detect overshoot in which the phase control signal rises above the high level; an overshoot canceller configured to lower the phase control signal which rises above the high level at an occurrence of the overshoot; and a phase interpolator configured to generate the clock by combining the plurality of phase clocks in accordance with the combining control signal.