A digital control device for a parallel PMOS transistor board, includes: an operative memory for digitally storing error data between a target voltage and a setpoint voltage as well as control data, each datum being provided with a time marker, a digital selected order filter (36) for computing setpoint incrementation data from error data in the operative memory selected based on input error data, and for storing the input error data with a corresponding time marker in the operative memory, and a control computer (38) for computing new control data from the control incrementation data and control data in the operative memory selected based on input error data and for storing the new control data in the operative memory.