Invention Grant
US09267990B2 CLK/TMS counter having reset output coupled to fourth count output
有权
CLK / TMS计数器具有耦合到第四计数输出的复位输出
- Patent Title: CLK/TMS counter having reset output coupled to fourth count output
- Patent Title (中): CLK / TMS计数器具有耦合到第四计数输出的复位输出
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Application No.: US14803645Application Date: 2015-07-20
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Publication No.: US09267990B2Publication Date: 2016-02-23
- Inventor: Gary L. Swoboda
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Frank D. Cimino
- Main IPC: G06F1/04
- IPC: G06F1/04 ; G06F5/00 ; G01R31/3177 ; G06F11/36 ; G06F11/27 ; G06F11/267 ; H04L12/26

Abstract:
Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.
Public/Granted literature
- US20150323599A1 ALTERNATE SIGNALING MECHANISM USING CLOCK AND DATA Public/Granted day:2015-11-12
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