A first indicator of a first number of cache misses to a cache memory of a multicore processor for a first application over a first time period is received. The first application executes on a first core of the processor and a second application simultaneously executes on a second core of the processor during the first time period. The first and second cores share the cache memory. A second indicator of a second number of cache misses to the cache memory for the first application over a second time period is received. During the second time period, the first application executes on the first core and the second application does not execute on the second core. A degree of contention among the first and second applications is determined based on the first and second indicators, and execution of the second application is adjusted based on the determined degree of contention.