Methods and systems to provide bit cell write-assist, including equalization of voltages of Bit and Bit nodes of a bit cell prior to a write operation. Equalization may be performed with a pulse-controlled transistor to transfer charge between the storage nodes. Pulse width and/or amplitude may be configurable, such as to scale with voltage. Bit cell write-assist may include reduction of bit cell retention strength during equalization, which may be continued during a write operation. Write-assist may be provided to each of multiple bit cells when a write operation is directed to a subset of the bit cells, which may conserve power and/or area. A partially-decoded address may be used to provide write-assistance to multiple bit cells prior to a write operation. Write-assistance may permit writing of Bit and Bit with a voltage swing significantly lower than an operating voltage of the bit cell.