Invention Grant
- Patent Title: Bipolar-MOS memory circuit
- Patent Title (中): 双极MOS存储电路
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Application No.: US14628925Application Date: 2015-02-23
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Publication No.: US09270269B2Publication Date: 2016-02-23
- Inventor: Daniel R. Shepard
- Applicant: HGST, Inc.
- Applicant Address: US CA San Jose
- Assignee: HGST, Inc.
- Current Assignee: HGST, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson & Sheridan, LLP
- Main IPC: G11C5/06
- IPC: G11C5/06 ; H03K19/00 ; H01L29/66 ; G11C11/412 ; G11C11/22 ; G11C11/4097 ; H03K19/094 ; H03K19/082 ; H03K19/0948 ; G11C11/06

Abstract:
Electronic memory circuits, and more particularly, low power electronic memory circuits having low manufacturing costs are disclosed. The present invention is a circuit design that utilizes two transistor types—bipolar and MOS (but, not both NMOS and PMOS) one of which can be manufactured together with the memory cell's non-linear conductive elements (such as a diode) thereby reducing the number of processing steps and masks and resulting in lower cost.
Public/Granted literature
- US20150171864A1 BIPOLAR-MOS MEMORY CIRCUIT Public/Granted day:2015-06-18
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