Invention Grant
US09274859B2 Multi processor and multi thread safe message queue with hardware assistance
有权
多处理器和多线程安全消息队列,具有硬件帮助
- Patent Title: Multi processor and multi thread safe message queue with hardware assistance
- Patent Title (中): 多处理器和多线程安全消息队列,具有硬件帮助
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Application No.: US11420394Application Date: 2006-05-25
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Publication No.: US09274859B2Publication Date: 2016-03-01
- Inventor: Gokhan Avkarogullari
- Applicant: Gokhan Avkarogullari
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F9/46 ; G06F9/54

Abstract:
A message exchange system for software components on different processors. A first component's attempt to load a write register with a message pointer (or a message itself) triggers a determination whether space exists in a shared memory queue. If so, the queue is updated by incrementing a message counter, writing the message/pointer into the queue where designated by a write pointer, and changing the write pointer to a next queue location. A second component's attempt to load the message/pointer from a read register triggers a determination whether there is at least one new message in the queue. If so, the queue is updated by decrementing the message counter, reading the message/pointer from the queue where designated by a read pointer, and changing the read pointer to point to a next queue location. The determinations and queue updates are performed atomically with respect to the software components.
Public/Granted literature
- US20070288931A1 MULTI PROCESSOR AND MULTI THREAD SAFE MESSAGE QUEUE WITH HARDWARE ASSISTANCE Public/Granted day:2007-12-13
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