The semiconductor memory device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal in response to a detection signal generated from detecting a level of a power supply voltage signal. The sense amplifier circuit may generate a first power signal driven to have a first drive voltage in response to the first power control signal. The sense amplifier circuit may sense and amplify a level of a bit line using the first power signal as a power supply voltage.