Invention Grant
US09275753B2 Circuit and method for reducing write disturb in a non-volatile memory device 有权
用于减少非易失性存储器件中的写入干扰的电路和方法

  • Patent Title: Circuit and method for reducing write disturb in a non-volatile memory device
  • Patent Title (中): 用于减少非易失性存储器件中的写入干扰的电路和方法
  • Application No.: US13896712
    Application Date: 2013-05-17
  • Publication No.: US09275753B2
    Publication Date: 2016-03-01
  • Inventor: Steven Smith
  • Applicant: SIDENSE CORP.
  • Applicant Address: CA Ottawa
  • Assignee: SIDENSE CORP.
  • Current Assignee: SIDENSE CORP.
  • Current Assignee Address: CA Ottawa
  • Agency: Borden Ladner Gervais LLP
  • Agent Shin Hung
  • Main IPC: G11C17/18
  • IPC: G11C17/18 G11C17/16
Circuit and method for reducing write disturb in a non-volatile memory device
Abstract:
An active precharge circuit for a non-volatile memory array which minimizes write disturb to non-selected memory cells during programming is disclosed. In a programming cycle, all bitlines are pre-charged to a program inhibit voltage level and held at the program inhibit voltage level with current or voltage sources coupled to each of the bitlines in a precharge operation and a following programming operation. In the programming operation, a bitline connected to a memory cell to be programmed is driven to a programming level, such as VSS, while the active precharge circuit is enabled to enable programming thereof. Because the other non-selected bitlines are held at the program inhibit voltage level, they will not be inadvertently programmed when the programming voltage is supplied by the word line.
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