Invention Grant
- Patent Title: Bead for 2.5D/3D chip packaging application
- Patent Title (中): 珠子用于2.5D / 3D芯片封装应用
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Application No.: US13481974Application Date: 2012-05-29
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Publication No.: US09275950B2Publication Date: 2016-03-01
- Inventor: Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Der-Chyang Yeh , Chuei-Tang Wang
- Applicant: Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Der-Chyang Yeh , Chuei-Tang Wang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/552 ; H01L23/522
Abstract:
An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters.
Public/Granted literature
- US20130320553A1 NOVEL BEAD FOR 2.5D/3D CHIP PACKAGING APPLICATION Public/Granted day:2013-12-05
Information query
IPC分类:
