- Patent Title: Integrated circuit process and bias monitors and related methods
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Application No.: US14808358Application Date: 2015-07-24
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Publication No.: US09276561B2Publication Date: 2016-03-01
- Inventor: Lawrence T. Clark , David A. Kidd , Chao-Wu Chen
- Applicant: MIE Fujitsu Semiconductor Limited
- Applicant Address: JP Kuwana, Mie
- Assignee: MIE Fujitsu Semiconductor Limited
- Current Assignee: MIE Fujitsu Semiconductor Limited
- Current Assignee Address: JP Kuwana, Mie
- Agency: Baker Botts L.L.P.
- Main IPC: H03K3/03
- IPC: H03K3/03 ; H03K3/011 ; G05F3/26 ; G05F3/20

Abstract:
An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.
Public/Granted literature
- US20150333738A1 Integrated Circuit Process and Bias Monitors and Related Methods Public/Granted day:2015-11-19
Information query
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