Invention Grant
- Patent Title: Semiconductor device and clock correction method
- Patent Title (中): 半导体器件和时钟校正方法
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Application No.: US14061605Application Date: 2013-10-23
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Publication No.: US09276586B2Publication Date: 2016-03-01
- Inventor: Tomoki Yasukawa
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2012-241624 20121101
- Main IPC: H03L7/00
- IPC: H03L7/00 ; H03K5/135

Abstract:
A frequency error calculator circuit calculates the frequency error in a basic clock based on the basic clock and on a reference clock having a frequency higher than the basic clock. An operation clock generator circuit outputs an operation clock whose error has been corrected based on the frequency error calculated by the frequency error calculator circuit. An ON/OFF control circuit outputs an ON/OFF control signal that specifies the calculation timing that the frequency error calculator circuit calculates the frequency error of the basic clock based on the frequency error calculated by the frequency error calculator circuit.
Public/Granted literature
- US20140118076A1 SEMICONDUCTOR DEVICE AND CLOCK CORRECTION METHOD Public/Granted day:2014-05-01
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