Invention Grant
US09276590B1 Generating signals with accurate quarter-cycle intervals using digital delay locked loop
有权
使用数字延迟锁定环生成具有精确四分之一周期间隔的信号
- Patent Title: Generating signals with accurate quarter-cycle intervals using digital delay locked loop
- Patent Title (中): 使用数字延迟锁定环生成具有精确四分之一周期间隔的信号
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Application No.: US14538088Application Date: 2014-11-11
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Publication No.: US09276590B1Publication Date: 2016-03-01
- Inventor: Guangjun He , Xiaojun Zhu
- Applicant: Ambarella, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Ambarella, Inc.
- Current Assignee: Ambarella, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Christopher P. Maiorana, PC
- Main IPC: H03L7/00
- IPC: H03L7/00 ; H03L7/08 ; H03L7/095
Abstract:
An apparatus comprising a delay circuit and a control circuit. The delay circuit may be configured to generate a plurality of intermediate signals in response to (i) a clock signal and (ii) an adjustment signal. The control circuit may be configured to generate the adjustment signal and a plurality of output signals having a quarter-cycle interval in response to (i) the plurality of intermediate signals and (ii) the clock signal.
Information query
