An AD converter includes a delta-sigma AD converter configured to receive an analog signal through an input terminal and obtain a higher-order bit conversion result, a first cyclic AD converter configured to receive a residual signal resulting from removal of a higher-order bit or bits, and performs a conversion process having a amplification factor of one to obtain a 1.5-bit conversion result, a second cyclic AD converter configured to perform a conversion process having an amplification factor of two to obtain a lower-order bit conversion result, and a shift register and a digital accumulator circuit that are configured to receive a higher-order bit, a 1.5-bit, and a lower-order bit conversion result and output an AD conversion value.