Invention Grant
- Patent Title: Vertical mount package and wafer level packaging therefor
- Patent Title (中): 垂直安装封装和晶圆级封装
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Application No.: US14484151Application Date: 2014-09-11
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Publication No.: US09278851B2Publication Date: 2016-03-08
- Inventor: Xiaojie Xue
- Applicant: ANALOG DEVICES, INC.
- Applicant Address: US MA Norwood
- Assignee: ANALOG DEVICES, INC.
- Current Assignee: ANALOG DEVICES, INC.
- Current Assignee Address: US MA Norwood
- Agency: Knobbe Martens Olson & Bear LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; B81B7/00 ; H01L21/50 ; H01L23/04 ; H01L23/498 ; H01L25/065 ; B81C1/00 ; H01L23/00

Abstract:
Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads.
Public/Granted literature
- US20140374854A1 VERTICAL MOUNT PACKAGE AND WAFER LEVEL PACKAGING THEREFOR Public/Granted day:2014-12-25
Information query
IPC分类: