Invention Grant
- Patent Title: Structures and methods for testing integrated circuits and via chains therein
- Patent Title (中): 用于测试集成电路和通孔链的结构和方法
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Application No.: US13875962Application Date: 2013-05-02
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Publication No.: US09279851B2Publication Date: 2016-03-08
- Inventor: Farkas Marton Csaszar
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G01R31/28 ; H01L21/66

Abstract:
An exemplary structure for testing an integrated circuit includes a semiconductor substrate and first and second via chains disposed over the substrate. The via chains include a substantially same sequence of segments interconnected at N via regions by a respective first and second via arrangement. The first via arrangement includes MN first vias at each respective via region and the second via arrangement includes MN+KN second vias at each respective via region. The first via arrangement is different than the second via arrangement and KN≧1 for at least one via region. The structure includes a voltage sensing apparatus in electrical connection with each via chain and configured to drive a first constant current through the first via chain and to drive a second constant current through the second via chain to measure a differential voltage between the via chains.
Public/Granted literature
- US20140327465A1 STRUCTURES AND METHODS FOR TESTING INTEGRATED CIRCUITS AND VIA CHAINS THEREIN Public/Granted day:2014-11-06
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