Invention Grant
- Patent Title: Data interface sleep mode logic
- Patent Title (中): 数据接口睡眠模式逻辑
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Application No.: US13537602Application Date: 2012-06-29
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Publication No.: US09280509B2Publication Date: 2016-03-08
- Inventor: Wei-Lien Yang
- Applicant: Wei-Lien Yang
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/04
- IPC: G06F1/04 ; G06F1/14 ; G06F13/42 ; G06F9/48 ; G06F1/32
Abstract:
In one embodiment, an apparatus may include a rising edge detector to detect a rising edge in a signal. The apparatus may also include a counter to perform a count to a first value based on an input clock signal. The apparatus may also include an output unit to generate a sleep signal after the first value is reached if the rising edge detector does not detect the rising edge in the signal.
Public/Granted literature
- US20140006840A1 DATA INTERFACE SLEEP MODE LOGIC Public/Granted day:2014-01-02
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