Disclosed herein is a semiconductor device that includes: a frequency dividing circuit dividing a frequency of a first clock signal to generate second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal; a data input/output terminal; data buses; and a data input/output circuit coupled between the data input/output terminal and the data buses. The data input/output circuit includes a data output circuit and a data input circuit. The data output circuit outputs read data supplied in parallel from the data buses to the data input/output terminal in serial in synchronism with the third clock signal. The data input circuit outputs write data supplied in serial from the data input/output terminal to the data buses in parallel in synchronism with a predetermined one of the second clock signals.