A system for testing a device under test (DUT) includes a test controller unit that includes a first memory operable to store a data pattern; a bridge circuit that includes a second memory that is smaller than the first memory, and a functional unit that includes a third memory that is smaller than the second memory. Portions of the data pattern are selectively transferred from the first memory to the second memory during and for DUT testing operations. The functional circuit interfaces with the DUT for testing. Portions of the data pattern are selectively transferred from the second memory to the third memory for application to the DUT.