Invention Grant
- Patent Title: CMOS gate stack structures and processes
- Patent Title (中): CMOS栅极堆叠结构和工艺
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Application No.: US14266115Application Date: 2014-04-30
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Publication No.: US09281248B1Publication Date: 2016-03-08
- Inventor: Thomas Hoffmann , Pushkar Ranade , Scott E. Thompson
- Applicant: MIE Fujitsu Semiconductor Limited
- Applicant Address: JP Kuwana, Mie
- Assignee: Mie Fujitsu Semiconductor Limited
- Current Assignee: Mie Fujitsu Semiconductor Limited
- Current Assignee Address: JP Kuwana, Mie
- Agency: Baker Botts L.L.P.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238

Abstract:
A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
Information query
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